SAA7391

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configurations is enabled
shadow = 1; enables shadowing for single drive configurations when the
SAA7391 is master and slave is non existent
shadow = 0; disables shadowing
7.5.3.21 HICONF1
This is the host interface configuration register 1.
Table 74 HICONF1: address FF95H (see Table 75)
ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RW dmaen shhpbit udmaoff flushfifo - unmaskdtei clear_reg ultractrl3
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Philips Semiconductors Objective specification
ATAPI CD-R block encoder/decoder SAA7391
Table 75 Description of the HICONF1 register bits
BIT NAME DESCRIPTION
7 dmaen DMA suspend: this bit controls whether DMA transfers in generic mode are suspended
dmaen = 1; host Interface DMA data transfers in generic can be temporarily interrupted
dmaen = 0; host Interface DMA data transfers in generic mode cannot be suspended
6 shhpbit this bit allows statistical host high priority to be turned off
shhpbit = 0; (default) statistical host high priority turned on
shhpbit = 1; statistical host high priority turned off
5 udmaoff this bit allows udma to be turned off at the end of a transfer
udmaoff = 0; (default) switch off the ultra_ata bit in the DTCTR register
udmaoff = 1; do nothing
4 flushfifo Flush 12-byte command FIFO: writing a logic 1 to this bit will flush clear the command
FIFO pointer to zero. Clearing the pointer is required if a spurious command is received
while the FIFO is being loaded and is also used to ensure a 12-byte command read by the
auto sequencer.
flushfifo = 1; writing a logic 1 clears the FIFO pointer to zero
flushfifo = 0; do nothing
2 unmaskdtei Unmask data transfer end interrupt during autodrq sequence: this bit will disable the auto
sequencer masking of the dtei interrupts during the autodrq sequence. The dtei , bit 6 of
the IFSTAT register is not effected by unmaskdtei . If unmaskdtei is asserted the
sequencer on detecting the next dtei interrupt, will set the bsy flag, negate the drq flag
and suspend operation. The microcontroller may then reconfigure the host interface
before negating unmaskdtei bit. When unmaskdtei is negated the sequencer will negate
the dtei interrupt and operate as normal.
unmaskdtei = 1; disable autodrq sequencer masking of dtei interrupts and suspend the
sequence operation on next dtei interrupt
unmaskdtei = 0; no effect, or restart autodrq sequencer operation
1 clear_reg Clear auto sequencer transfer counter and packet size store to zero: this bit will clear the
transfer counter and packet size store to zero if a logic 1 is written to it. After the write
operation the registers operate as normal and the clear_reg bit will have no effect unless
written to again.
clear_reg = 1; clears to zero transfer counter and packet size store
clear_reg = 0; no effect
0 ultractrl3 ultra control bit 3; see Section 7.5.3.22
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Philips Semiconductors Objective specification
ATAPI CD-R block encoder/decoder SAA7391
When the SAA7391 system clock is 33.8688 MHz,
7.5.3.22 Description of the ultra control bits
maximum data transfer rates in ultra DMA Mode 0 are
The ultractrl register bits can be used to add system clock
achieved by setting ultractrl to (0001).
cycles to various timing limits used in the host interface
For information on meeting Mode 0 timings for system
ultra DMA transfer engine.
clocks other than 33.8688 MHz, please consult the user
This enables the SAA7391 to meet ultra DMA Mode 0
manual or product support.
timings when the SAA7391 system clock is higher than
33.8688 MHz.
7.5.3.23 HISEQ
Table 76 HISEQ: host interface sequencer register; address FF96H (see Table 77)
ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RW autoa0 autodrq comp error sus_seq repeat autoa0 - -
Table 77 Description of the HISEQ register bits
BIT NAME DESCRIPTION
7 autoa0 automatic A0 packet transfer enable: this bit enables the sequencer to automatically
handle transfer of A0 packet bytes
autoa0 = 1; enables automatic transfer of A0 packet bytes
autoa0 = 0; disables automatic transfer of A0 packet bytes
6 autodrq enables the auto data request sequence: this bit enables automatic handling of data
requests in PIO and DMA mode transfers
autodrq = 1; auto sequencer is enabled to perform auto data requests
autodrq = 0; auto sequencer is not enabled to perform auto data request
5 comp Completion sequence for autodrq : this bit indicates that the auto completion sequence
should be performed after the last data transfer. This bit is only valid when the auto
sequencer is enabled.
comp = 1; enable the auto sequencer to automate the completion sequence
comp = 0; disable the auto completion sequence
4 error completion sequence with error status: this bit is copied to the check bit of the ASTAT
register just before an auto completion sequence is performed
error = 1; completion sequence with error status in check bit of ASTAT
error = 0; completion without error status
3 sus_seq Suspend auto sequence: this bit suspends the auto sequencer for debug. If the
suspend state is a write to register state then the write operation will only take place
when after the sus_seq bit is negated.
sus_seq = 1; suspend sequencer in present state
sus_seq = 0; normal sequence operation
2 repeat autoa0 Repeat the A0 packet reception auto sequence after an autodrq or auto completion
sequence. This bit, if set before an autodrq or auto completion sequence, will be
copied to autoa0 bit when the sequencer is reset at the end of an autodrq or auto
completion sequence. This bit is negated at the end of the autoA0 sequence. Its effect
is to repeat the autoA0 sequence one more time only. It should be noted that this bit is
only available on RODAP and not the M1 data base.
repeat autoa0 = 1; repeat autoA0 sequencer after autodrq or auto completion
repeat autoa0 = 0; no effect
1997 Aug 01 46
Philips Semiconductors Objective specification
ATAPI CD-R block encoder/decoder SAA7391
7.5.3.24 SHSTAT
Table 78 SHSTAT: shadow status register; address FF97H
ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
W 0 0 0 0 0 0 0 shcheck(1)
Note
1. Shadow check bit: shcheck is the ATAPI CHECK bit in the slave shadow status register for the non-existent drive.
a) 1 = Indicates an error has occurred.
b) 0 = Indicates no error has occurred.
7.5.3.25 SHERR
Table 79 SHERR: shadow error register; address FF98H
ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
W 0 0 0 0 0 shabrt(1) 0 0
Note
1. Shadow abort bit: shabrt is the ATAPI abrt bit in the slave shadow error register for the non-existent drive. This bit
will be read by the host in shadow mode only.
a) 1 = indicates requested command has been aborted.
b) 0 = indicates requested command successful.
7.5.3.26 HIDEV
Table 80 HIDEV: host interface device register; address FF99H (see Table 81)
ACCESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
RW pdiag out pdiag dasp out dasp pdiag in dasp in - hosthipi
enable enable
1997 Aug 01 47
Philips Semiconductors Objective specification
ATAPI CD-R block encoder/decoder SAA7391
Table 81 Description of the HIDEV register bits
BIT NAME DESCRIPTION
7 pdiag out this bit is the passed diagnostics signal output from the SAA7391
pdiag out = 1; writing logic 1 to this bit drives the PDIAG pin HIGH if the pad enable
( pdiag enable bit 6) is set to logic 1. It is recommended that this bit is written LOW and
that the enable bit is driven to emulate an open-collector output.
pdiag out = 0; writing logic 0 to this bit sets the PDIAG pin LOW if the pad enable
( pdiag enable bit 6) is set to logic 1
6 pdiag pad this bit default is an input to the SAA7391
enable
pdiag pad enable = 1; writing logic 1 to this bit enables the PDIAG driver output of the [ Pobierz całość w formacie PDF ]

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